Package Substrate

The product is a package substrate that is used for the core semiconductors of mobile devices and PCs. It transmits electric signals between semiconductors and the main board, and protects expensive semiconductors from external stress. Compared with general substrates, as this substrate is a high-density circuit substrate containing more microcircuits, the assembly defects and incurred costs in directly bonding expensive semiconductors to the substrate can be reduced.

FCCSP(Flip Chip Chip Scale Package)

This is called Flip Chip Chip Scale Package (FCCSP) as semiconductor chips are upturned and connected to a board through a bump rather than wire bonding. It is mainly used for the application processor (AP) chips of mobile IT devices. Also Compared to WBCSP using Gold Wire, the process using Flip Chip can be applied to high-density semiconductors because the route of electrical signals is shorter, and larger input and output can be accommodated.

Application
Mobile Application Processor, Baseband and Others
Semiconductor Chip -> Bumping(Solder) -> Flip -> Packaging(PCB)

Key Core Technologies

1. Bumping Structure

Bumping Structure

2. μBall Bump Method

μBall Bump Method

  • Available for Fine Bump Pitch
  • Good for Small Bump Risk
  • Good Quality for Bump Characteristics

Substrate Type

1. EPS (Embedded Passive Substrate) &
EDS (Embedded Die Substrate)

EPS/EDS is a substrate that can be mass-produced by embedding semiconductor passive elements and the IC, among other components, inside the board.
Decoupling capacitors are typically used to stabilize power supply voltage levels.By embedding the IC inside the board, package size and thickness can be reduced.

EPS, EDS
2. ETS(Embedded Trace Substrate)

ETS is a circuit board whose circuit pattern is in the insulating material. ETS has a coreless structure, which allows for the implementation of microcircuits without the need for additional cost. Layer Down is performed much easier (4L → 3L). Also As the etching process is not affected by the pattern width, the circuit width can be precisely controlled.

[2Layer Buried Trace], [3Layer Buried Trace], [4Layer Buried Trace]

Lineup

Lineup by Specification

Mass Production Sample Available

Lineup by Specification Explanation Explanation for Routing Density, Build-Up Line Width / Space.
Routing Density Build-Up Line Width / Space 7 / 8um 6 / 7um
BVH / Pad Registration 40 / 67um 37 / 60um
SRO Diameter
SR Registration
45 ± 10um 40 ± 10um
FC Bump Pitch (Peripheral) 40um 35um
FC Bump Pitch (Area) 90um 80um
Low Z-Height Core / PPG Thickness 40 / 18um 35 / 15um
SR Thickness 10 ± 4um 8 ± 3um

WBCSP(Wire Bonding Chip Scale Package)

This is a semiconductor chip the size of which is more than 80% of that of the finished part. It is called WBCSP (Wire Bonding CSP) because a gold wire bonding method is applied to connect the semiconductor chip and the PCB.
A gold wire is used to connect the chip and PCB, and multi-packaging is possible, which makes the product mainly applicable for memory chips. In particular, UTCSP (Ultra Thin CSP) products are made with a thickness of 0.13mm or thinner. With a high degree of freedom in the chip to PCB connection, multi-chip packaging is made possible, and better performance is realized compared with other products of the same thickness.

Application
Mobile Equipment Memory

Lineup

Lineup by Specification

General WBCSP Road Map of HVM / Sample Product

Mass Production Sample Available
Lineup by Specification Explanation Explanation for Routing Density, Bond Finger Pitch.
Routing Density Bond Finger Pitch 55P (25 / 12, Ni 3) (Mass Production) 50P (20 / 10, Ni 2) (Sample Available)
Line Width / Space mSAP
(Cu T 14)
12 / 16um(Mass Production) 10 / 15um(Sample Available)
ETS
(Cu T 13)
7 / 8um (Mass Production) 6 / 7um (Sample Available)
Via / Pad Size mSAP 50 / 90um(Mass Production) 45 / 85um(Sample Available)
ETS 40 / 65um (Mass Production) 37 / 60um (Sample Available)
SRO alignment ± 12.5um (Mass Production) ± 10um (Sample Available)
Min. SR Open size 45um (Mass Production) 40um (Sample Available)
Lineup by Structure & Z-Height
Mass Production Sample Available
Lineup by Structure & Z-Height Layer, Structure, Thickness etc.
Layer count Structure Thickness
2Layer (Mass Production) Cored (Mass Production) 80um (Mass Production) 75um
3Layer (Mass Production) Coreless (Mass Production) 80um (Mass Production) 75um
ETS (Mass Production) 120um (Mass Production) 100um
4Layer (Mass Production) Cored (Mass Production) 120um (Mass Production) 110um
Coreless (Mass Production) 110um (Mass Production) 100um
ETS (Mass Production) 160um (Mass Production) 140um
6Layer (Mass Production) Cored (Mass Production) 220um (Mass Production) 180um
Coreless (Mass Production) 200um (Mass Production) 180um

SiP(System in Package)

This product is developed by realizing complex functions into one system by mounting multiple ICs and passive components in a package. It is also used in products such as Power Amplifiers (PA) and has heat dissipation characteristics. The product series include Flip-Cip SiP and Coreless.

Application
PA(Power Amplifier), PAMID (Power Amplifier Module with Integrated Duplexer), FEMID(Front-End Module with Integrated Duplexer), SAW Filter, BAW Filter, Various RF Parts like Diversity FEM and Switch

Features

1. Miniaturization

Can realize small packages as multiple ICs and passive components are integrated into one module.

[SiP Composition Shape]
  • 1. Sip
  • 2. Die 1
  • 3. Die 2
  • 4. Die 3
2. Thin Substrate

Can realize 0.2mm thin substrate (based on a 6-layer substrate) by securing the driving capability of ultrathin sheets.

[ 0.2T 6L RF-SiP ](200um), [ 10L ~, 5G Antenna Module ]

Key Core Technologies

1. Coreless RF-SiP

Signal characteristics can be enhanced by controlling Electromagnetic Interference (EMI) and the parasitic inductance by lowering the insulation thickness through the application of the coreless method. This serves as the basis for materializing thin substrates.

Cored Substrate, Coreless Substrate *Thin substrate Can realize
2. ENEPIG Surface Treatment

The ENEPIG surface treatment technology has the following characteristics.

1) Thin Ni ENEPIG

- RF performance is possible based on the Ni thickness.

Ni Thickness 0.1um ENIG/ENEPIG →  Ni Thickness 0.1um Thin Ni ENEPIG
Ni Thickness 0.1um ENIG/ENEPIG
Gold, Nickel, Copper, Palladium
Ni Thickness 0.1um Thin Ni ENEPIG
Gold, Nickel, Palladium, Copper
  • * ENIG : Electroless Nickel Immersion Gold
  • * ENEPIG : Electroless Nickel Electroless Palladium Immersion Gold
2) Selective ENEPIG

- Selective ENEPIG allows the treatment of different surface types on the same board. (ENEPIG + OSP)

2) Selective ENEPIG allows the treatment of different surface types on the same board. (ENEPIG + OSP)
ENEPIG + OSP
ENEPIG, OSP
  • * OSP : Organic Solderability Preservative

Lineup

Lineup by Specification
Mass Production Sample Available
Lineup by Specification Explanation Explanation for Layer Structure, Cored.
Layer Structure Cored 2L / 4L / 6L / 8L / 10L + 12L / 14L
Coreless 5L / 6L / 7L / 8L + 4L / 9L / 10L
Line Width / Space 12 / 16um 10 / 15um
Bump Pitch 130um 105um
Surface Finish Direct Au, Thin ENEPIG, Selective ENEPIG Direct Au, Thin ENEPIG, Selective ENEPIG

FCBGA(Flip Chip Ball Grid Array)

The product is a high-density package substrate that is used to connect a high-integration semiconductor chip to a main board. The semiconductor chip and the package substrate are connected with Flip Chip Bump, and fine matching between layers is required due to the miniaturization of the substrate circuit and high multi-layer. In particular, Large Body Size and high multi-layer (~75x75㎜, 20L) technology are required to respond to High Performance Computing.

Application
CPU, GPU, Server CPU, AI Accelerator, Automotive, Network, Game Console, D-TV
FCBGA(Flip Chip Ball Grid Array) [1.Solder Ball, 2.Solder Bump, 3.Pattern, 4.Chip]

Lineup

FCB is available in Standard Core, Thin Core type products.
Mass Production Sample Available
Lineup FCB Explanation Explanation for Core Thickness, Line Width/Space Bump Pitch(Mass Volume).
Core Thickness (um) Line
Width
/Space
Bump
Pitch
(Mass
Volume)
Layer Counts
4L 6L 8L 10L 12L 14L 16L 18L 20L 22L
Standard Core 1200 9 / 12um
90um
                   
800                    
600                    
400                    
Thin Core 250 9 / 12um
100um
                   
200                    
100                    

*um stands for ㎛

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